A Medium-Format, Mixed-Mode Pixel Array Detector for Kilohertz X-ray Imaging

An x-ray pixel array detector (PAD) capable of framing up to 1 kHz is described. This hybrid detector is constructed from a 3-side buttable, 128×128 pixel module based upon the mixed-mode pixel array detector (MMPAD) chip developed jointly by Cornell and Area Detector Systems Corporation (Poway, CA). The chip uses a charge integrating front end for a high instantaneous count rate yet with single photon sensitivity. In-pixel circuitry utilizing a digital overflow counter extends the per frame dynamic range to >4×10 x-rays/pixel. Results are shown from a base configuration of a 2×3 module array (256×384 pixels). 1. Mixed-mode PAD architecture Pixel array detectors (PADs) can be classified according to the front end circuitry. Photon counting PADs [1,2] image with pulse height thresholding and an in-pixel counter. Dark noise is rejected but pixel count rates are typically limited to ca. 106 Hz. Analog PADs [3-6] use charge integration over the framing period. Since individual x-ray pulses need not be resolved, the maximum photon rate is increased substantially. Single x-rays can be detected if a small integration capacitance is used but well depth is limited to ca. 104 x-rays per pixel even for large capacitances. An alternative approach is implemented in the mixed-mode PAD (MMPAD) (figure 1), developed in a collaboration between Cornell and Area Detector Systems Corporation [7-8]. When a comparator threshold is exceeded during integration, a charge removal circuit and an 18 bit overflow counter are triggered. This keeps the integrator in its operating region and extends the dynamic range by 2 18. A small integration capacitance gives high sensitivity to single x-rays. The average sustained photon rate is limited by the time required for a charge removal step, but that average rate is an order of magnitude higher than typical in a photon counting detector. Note the temporally bunched structure of a synchrotron beam can give instantaneous photon rates many orders of magnitude higher than the average rate (when ≥ 2 photons arrive from any single bunch). The MMPAD integrating architecture can correctly record 200 photons arriving instantaneously, limited by the charge removal step size. 2. Detector construction This detector is constructed from 6 single-chip tiles arranged in a 2×3 array as seen in figure 2. Each 3side buttable tile has 128×128 pixels with a 150 μm pitch. Each MMPAD chip is bump-bonded pixel11th International Conference on Synchrotron Radiation Instrumentation (SRI 2012) IOP Publishing Journal of Physics: Conference Series 425 (2013) 062004 doi:10.1088/1742-6596/425/6/062004 Published under licence by IOP Publishing Ltd 1 by-pixel to a fully-depleted detector diode layer fabricated in 500 μm thick, high-resistivity silicon and biased to 150 V. Figure 1. MMPAD pixel schematic. Comparator threshold, Vth, triggers counter and removes a charge, ∆Q, from the input. Digital counter and analog remainder are read at frame end. Figure 2. MMPAD 2×3 module assembly. 6-chip imaging array at center with 3 sets of circuit boards extending to each side and then downward. Shown with front vacuum window removed. Each module assembly consists of a pair of small circuit boards mounted on a heatsink along with an MMPAD chip. The circuit boards provide signal buffering and analog-to-digital conversion. Six assemblies are aligned and mounted on a thermoelectrically controlled (-30 C) aluminum block. Module spacing is set nominally to be an integer number of pixels. A common backplane board provides vacuum feedthrough for all signals. An FPGA board (Xilinx Virtex-6 ML605) controls the chip clocking and data capture. Output is read through 48 analog and 48 digital output channels. Analog remainder values are digitized to 12 bits. The FPGA handles the necessary bit reordering, including passage of the 18 bit digital word through a look-up-table to decode the counter value from its pseudo-random shift register implementation [7,8]. The digital data is scaled and added to the analog data to form a 32 bit word. Data is transferred to the host computer via a CameraLink interface (Matrox Radient eCL). Frame readout occurs in 0.86 ms. Host PC software places tiles within the frame and performs background subtraction. A live display window and region of interest calculations are provided. Integration timing is set using a 36-bit programmable counter in the FPGA. Framing modes include single frame, a set of N sequential frames, and continuous framing. Frames can be initiated via ethernet commands or an external hardware trigger. Sustained frame rates to 1100 Hz can be achieved to computer memory and up to 200 Hz for continuous storage to disk. Note the maximum signal/pixel for short integration times will be subject to the sustained count rate limit of >108 Hz/pixel. Table 1. Detector performance parameters Pixel size 150 μm Read noise (rms) 0.16 x-rays (8 keV) Detector format (2×3 chip) 256 × 384 pixels Full well 4.7×107 x-rays (8 keV) Instantaneous count rate >1012 Hz/Pixel Sustained count rate >108 Hz/pixel Read time 0.86 ms Energy Range 1 – 20 keV 3. Detector Characterization Detector characterizations (Table 1) were made using a low power copper x-ray source (Tru-Focus TCM-5000M) placed 40 cm from the detector to provide a uniform source of illumination. The x-ray spectrum was made roughly monochromatic by using tube biases below 14 kV along with a 25 μm thick nickel filter. An array of 75 μm holes at 450 μm pitch fabricated in 50 μm thick tungsten foil 11th International Conference on Synchrotron Radiation Instrumentation (SRI 2012) IOP Publishing Journal of Physics: Conference Series 425 (2013) 062004 doi:10.1088/1742-6596/425/6/062004